The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 16, 2021

Filed:

Aug. 08, 2019
Applicant:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Inventors:

Remi Coquand, Grenoble, FR;

Shay Reboh, Grenoble, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/225 (2006.01); H01L 21/306 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66742 (2013.01); H01L 21/2254 (2013.01); H01L 21/30604 (2013.01); H01L 29/6653 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/78648 (2013.01); H01L 29/78696 (2013.01);
Abstract

A method is provided for fabricating a double gate structure for transistors with superposed bars, including: providing, on a support, a stack including an alternation of one or several first bars based on a first semiconducting material, and one or several second bars based on a second semiconducting material; removing lateral portions of the second bars; forming insulating plugs in contact with lateral regions of the second bars; removing the first bars; and forming a gate electrode facing an upper face and a lower face of the second bars, the insulating plugs being arranged in contact with the lateral regions of the second bars when the gate electrode is being formed.


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