The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 16, 2021

Filed:

Mar. 06, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Kuo-Yen Liu, Hsinchu County, TW;

Boo Yeh, Hsinchu, TW;

Min-Chang Liang, Hsin-Chu County, TW;

Jui-Yao Lai, Changhwa, TW;

Sai-Hooi Yeong, Zhubei, TW;

Ying-Yan Chen, Hsinchu, TW;

Yen-Ming Chen, Chu-Pei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 23/528 (2006.01); H01L 23/52 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 21/76807 (2013.01); H01L 21/76816 (2013.01); H01L 23/52 (2013.01); H01L 23/528 (2013.01); H01L 23/5283 (2013.01); H01L 23/5329 (2013.01); H01L 23/53295 (2013.01); H01L 21/76895 (2013.01); H01L 23/53209 (2013.01); H01L 23/53214 (2013.01); H01L 23/53228 (2013.01); H01L 23/53242 (2013.01); H01L 23/53257 (2013.01);
Abstract

A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias.


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