The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 16, 2021
Filed:
Sep. 11, 2018
Applied Materials, Inc., Santa Clara, CA (US);
Pramit Manna, Santa Clara, CA (US);
Abhijit Basu Mallick, Fremont, CA (US);
Kurtis Leschkies, San Jose, CA (US);
Steven Verhaverbeke, San Francisco, CA (US);
Shishi Jiang, Santa Clara, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
Methods for forming a semiconductor structure including a silicon (Si) containing layer or a silicon germanium (SiGe) layer are provided. The methods include depositing a protective barrier (e.g., liner) layer over the semiconductor structure, forming a flowable dielectric layer over the liner layer, and exposing the flowable dielectric layer to high pressure steam. A cluster system includes a first deposition chamber configured to form a semiconductor structure, a second deposition chamber configured to perform a liner deposition process to form a liner layer, a third deposition chamber configured to form a flowable dielectric layer over the liner layer, an annealing chamber configured to expose the flowable oxide layer to high pressure steam.