The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 16, 2021

Filed:

Mar. 27, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

David M. Durham, Beaverton, OR (US);

Siddhartha Chhabra, Portland, OR (US);

Amy L. Santoni, Scottsdale, AZ (US);

Gilbert Neiger, Portland, OR (US);

Barry E. Huntley, Hillsboro, OR (US);

Hormuzd M. Khosravi, Portland, OR (US);

Baiju V. Patel, Portland, OR (US);

Ravi L. Sahita, Portland, OR (US);

Gideon Gerzon, Zichron Yaakov, IL;

Ido Ouziel, Ein Carmel, IL;

Ioannis T. Schoinas, Portland, OR (US);

Rajesh M. Sankaran, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/14 (2006.01); G06F 21/53 (2013.01); G06F 21/78 (2013.01); G06F 21/60 (2013.01); G06F 21/82 (2013.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1408 (2013.01); G06F 3/0623 (2013.01); G06F 12/145 (2013.01); G06F 21/53 (2013.01); G06F 21/602 (2013.01); G06F 21/78 (2013.01); G06F 21/82 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/401 (2013.01); G06F 2212/402 (2013.01);
Abstract

In one embodiment, an apparatus comprises a processor to read a data line from memory in response to a read request from a VM. The data line comprises encrypted memory data. The apparatus also comprises a memory encryption circuit in the processor. The memory encryption circuit is to use an address of the read request to select an entry from a P2K table; obtain a key identifier from the selected entry of the P2K table; use the key identifier to select a key for the read request; and use the selected key to decrypt the encrypted memory data into decrypted memory data. The processor is further to make the decrypted memory data available to the VM. The P2K table comprises multiple entries, each comprising (a) a key identifier for a page of memory and (b) an encrypted address for that page of memory. Other embodiments are described and claimed.


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