The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 2021

Filed:

Jun. 08, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Eng Huat Goh, Ayer Itam, MY;

Min Suet Lim, Bayan Lepas, MY;

Tin Poay Chuah, Bayan Baru, MY;

Han Kung Chua, Bayan Lepas, MY;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/00 (2006.01); H05K 3/46 (2006.01); H05K 1/02 (2006.01); H05K 1/18 (2006.01); H05K 3/30 (2006.01);
U.S. Cl.
CPC ...
H05K 3/4611 (2013.01); H05K 1/028 (2013.01); H05K 1/181 (2013.01); H05K 1/189 (2013.01); H05K 3/303 (2013.01); H05K 3/4602 (2013.01); H05K 2201/091 (2013.01); H05K 2201/09118 (2013.01); H05K 2201/10378 (2013.01); H05K 2201/10522 (2013.01); H05K 2201/10545 (2013.01);
Abstract

Disclosed herein is a multi-planar circuit board, as well as related structures and methods. In an embodiment, a circuit board may include a first surface, a first section having the first surface in a first plane, a second section having the first surface in a second plane, and a third section connecting the first and second sections, where the third section defines a gradient between the first and second planes, and where all sections are sections within a contiguous board. In another embodiment, circuit board may further include a first component having a first thickness coupled on the first face of the first section, and a second component having a second thickness, greater than the first component, coupled on the first face of the second section, where the second section is in a lower plane, and where the overall thickness is the circuit board thickness plus the second thickness.


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