The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 2021

Filed:

Dec. 13, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Gyu Jin Choi, Suwon-si, KR;

Sung Hoan Kim, Suwon-si, KR;

Chang Eun Joo, Suwon-si, KR;

Chil Woo Kwon, Suwon-si, KR;

Young Kyu Lim, Suwon-si, KR;

Sung Uk Lee, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/13 (2006.01); H01L 23/31 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 24/16 (2013.01); H01L 23/13 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 23/49894 (2013.01); H01L 24/13 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 24/96 (2013.01); H01L 2224/13006 (2013.01); H01L 2224/16235 (2013.01);
Abstract

A semiconductor package includes: a semiconductor chip including a body having a first surface and a second surface, opposing the first surface, a connection pad disposed on the first surface of the body, and an extension pad disposed on the connection pad; and a connection structure including an insulating layer disposed on the first surface of the body of the semiconductor chip, a redistribution via penetrating through the insulating layer and having one side thereof in contact with the extension pad, and a redistribution layer disposed on the insulating layer and having a via pad in contact with the other side of the redistribution via, wherein a horizontal cross-sectional area of extension pad of the semiconductor chip is greater than a horizontal cross-sectional area of the connection pad of the semiconductor chip.


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