The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 2021

Filed:

Nov. 25, 2019
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Shih-Cheng Chen, Tainan, TW;

Li-Hsuan Ho, Kaohsiung, TW;

Tsuo-Wen Lu, Kaohsiung, TW;

Shih-Hao Liang, Tainan, TW;

Tsung-Hsun Wu, Kaohsiung, TW;

Po-Jen Chuang, Kaohsiung, TW;

Chi-Mao Hsu, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/535 (2006.01); H01L 27/092 (2006.01); H01L 23/528 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 23/535 (2013.01); H01L 21/28088 (2013.01); H01L 21/82385 (2013.01); H01L 21/823871 (2013.01); H01L 23/528 (2013.01); H01L 27/092 (2013.01); H01L 29/4966 (2013.01); H01L 29/66545 (2013.01);
Abstract

A semiconductor device includes a substrate having a NMOS region and a PMOS region; a gate structure extending along a first direction from the NMOS region to the PMOS region on the substrate; and a first contact plug landing directly on the gate structure closer to the PMOS region from a boundary separating the NMOS region and the PMOS region. Preferably, the semiconductor device further includes a first source/drain region extending along a second direction adjacent to two sides of the gate structure on the NMOS region and a second source/drain region extending along the second direction adjacent to two sides of the gate structure on the PMOS region.


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