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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11171080 B1

PDFFull Text
Date of Patent:
Nov. 09, 2021

Filed:

Oct. 16, 2019

Wiring substrate

Applicant:

Shinko Electric Industries Co., Ltd., Nagano, JP;

Inventors:

Takahiko Kiso, Nagano, JP;

Masahiro Kyozuka, Nagano, JP;

Assignee:

SHINKO ELECTRIC INDUSTRIES CO., LTD., Nagano, JP;

Attorney:

Rankin, Hill & Clark LLP

Primary Examiner:

Steven B Gauthier

Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/13 (2006.01); H01L 23/31 (2006.01); H01L 23/367 (2006.01); H01L 23/29 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/373 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49822 (2013.01); H01L 21/486 (2013.01); H01L 21/4857 (2013.01); H01L 21/565 (2013.01); H01L 23/13 (2013.01); H01L 23/295 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 23/3675 (2013.01); H01L 23/3737 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 23/49894 (2013.01); H01L 23/5389 (2013.01); H01L 23/49816 (2013.01); H01L 24/16 (2013.01); H01L 2224/16227 (2013.01);
Abstract

A wiring substrate includes a first insulation layer, an electronic component including a first surface and a second surface which is an opposite surface to the first surface, the electronic component being mounted on the first insulation layer with the first surface facing toward the first insulation layer, and a second insulation layer including a first layer and a second layer. The first layer is formed on the first insulation layer and configured to cover the second surface of the electronic component, and the second layer is stacked on the first layer. The first layer includes therein fillers. At least one of the fillers is in direct contact with the second surface of the electronic component at one side, and is exposed from the first layer and is thus in direct contact with the second layer at the other side.

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