The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 2021

Filed:

Mar. 01, 2017
Applicant:

Telefonaktiebolaget Lm Ericsson (Publ), Stockholm, SE;

Inventors:

Neng Liu, Montreal, CA;

Robert Brunner, Montreal, CA;

Stephane Lessard, Mirabel, CA;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/473 (2006.01); H01L 21/48 (2006.01); H01L 25/16 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/473 (2013.01); H01L 21/4882 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/167 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01);
Abstract

An electronic-photonic integrated-circuit assembly comprises a carrier substrate () and one or more integrated-circuit dies () bonded to one another so as to form a die stack with exterior surfaces corresponding to an outer surface of a first one of the integrated-circuit dies and to an outer surface of a second one of the integrated-circuit dies, where at least one of the integrated-circuit dies includes one or more integrated photonic devices. One or more channels or passages () are formed into the outer surface of the first one of the integrated-circuit dies, and a first surface of the carrier substrate () is bonded to the outer surface of the first one of the integrated-circuit dies, thereby enclosing the one or more channels or passages (), The integrated-circuit dies are electrically connected to each other via electrically conductive through-wafer interconnects or electrically conductive through-wafer vias.


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