The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 2021

Filed:

Jan. 16, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Namho Jeon, Hwaseong-si, KR;

Joonyoung Choi, Suwon-si, KR;

Jiyoung Kim, Yongin-si, KR;

Junsoo Kim, Seongnam-si, KR;

Dongsoo Woo, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 27/12 (2006.01); H01L 21/84 (2006.01); H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76283 (2013.01); H01L 21/84 (2013.01); H01L 27/10876 (2013.01); H01L 27/1203 (2013.01);
Abstract

A fabrication method of an integrated circuit semiconductor device includes: forming a plurality of low dielectric pattern apart from each other on a substrate, the plurality of low dielectric pattern having a lower dielectric constant than the substrate; after forming the low dielectric pattern, forming a flow layer to bury the low dielectric pattern on the substrate; forming an epitaxial layer on the flow layer; and forming a transistor in the substrate comprising the low dielectric pattern buried by the flow layer and in the epitaxial layer.


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