The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 2021

Filed:

Jul. 27, 2020
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventors:

Chia-Fu Chang, Hsinchu County, TW;

Hung-Yi Liao, Hsinchu County, TW;

Assignee:

EMEMORY TECHNOLOGY INC., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/04 (2006.01); G11C 16/30 (2006.01); G11C 16/08 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3481 (2013.01); G11C 16/0433 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/30 (2013.01);
Abstract

A non-volatile memory includes a cell array, a current supply circuit, a path selecting circuit and a verification circuit. The cell array includes plural multi-level memory cells in an m×n array. The cell array is connected with m word lines and n lines. Each of the plural multi-level memory cells is in one of X storage states. The current supply circuit provides plural reference currents. The path selecting circuit is connected with the current supply circuit and the n bit lines. The verification circuit is connected with the path selecting circuit, and generates n verification signals. A first path selector of the path selecting circuit is connected with a path selecting circuit and a first bit line. A first verification device of the verification circuit is connected with the first path selector and generates a first verification signal.


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