The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 2021

Filed:

Apr. 28, 2020
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Daniel S. Miller, Boise, ID (US);

Yoshinori Fujiwara, Boise, ID (US);

Assignee:

Micron Technology, Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/22 (2006.01); G11C 11/4096 (2006.01); G11C 29/04 (2006.01); G11C 11/4094 (2006.01);
U.S. Cl.
CPC ...
G11C 11/2275 (2013.01); G11C 11/221 (2013.01); G11C 11/2255 (2013.01); G11C 11/2273 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01); G11C 29/04 (2013.01);
Abstract

Methods, systems, and devices related to identifying high impedance faults in a memory device are described. A memory device may perform a first write operation to write a first logic state to a memory cell. During the first write operation, the memory device may establish a connection between a supply line and a control line associated with applying an output of a driver of a digit line coupled to the memory cell. After performing the first operation, the memory device may configure the supply line in a floating state. After the supply line is floated, the memory device may perform a second write operation to write a second logic state to the memory cell. The memory device may perform a third operation for reading the memory cell. The memory device may determine the condition of the supply line or control based on the result of the read operation.


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