The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 02, 2021

Filed:

Jul. 08, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventor:

Qinglei Zhang, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 7/10 (2006.01); H05K 7/12 (2006.01); H05K 3/24 (2006.01); H05K 3/28 (2006.01); H01L 23/13 (2006.01); H01L 21/48 (2006.01); H05K 3/34 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H05K 3/244 (2013.01); H01L 21/4857 (2013.01); H01L 23/13 (2013.01); H05K 3/282 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/81444 (2013.01); H01L 2224/81801 (2013.01); H01L 2924/12042 (2013.01); H05K 3/3436 (2013.01); H05K 2201/0376 (2013.01); H05K 2201/10378 (2013.01); H05K 2201/10734 (2013.01); H05K 2203/025 (2013.01); H05K 2203/1476 (2013.01); H05K 2203/1572 (2013.01);
Abstract

Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first surface finish on one or more electrical routing features located on a first side of a package substrate and on one or more lands located on a second side of the package substrate, the second side being opposite the first side of the substrate. The method may further include removing the first surface finish on the first side of the package substrate; and depositing a second surface finish on the one or more electrical routing features of the first side. The depositing of the second surface finish may be accomplished by one of a Direct Immersion Gold (DIG) process or an Organic Solderability Preservative (OSP) process. Other embodiments may be described and/or claimed.


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