The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 02, 2021

Filed:

Sep. 11, 2020
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Loren B. Reiss, Raleigh, NC (US);

Scott David Huss, Cary, NC (US);

Christopher George Moscone, Cary, NC (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/033 (2006.01); H04L 7/00 (2006.01); H04L 1/24 (2006.01); H03L 7/081 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0025 (2013.01); H03L 7/0812 (2013.01); H04L 1/243 (2013.01); H04L 7/0337 (2013.01);
Abstract

A phase interpolator of a physical layer (PHY) device comprise a phase interpolator to generate a set of asynchronous sampler clocks. A sampler of the PHY device samples a calibration data pattern using a first sampler clock from the set of asynchronous sampler clocks. A calibration control component of the PHY device detects a misalignment of a phase relationship among the set of asynchronous sampler clocks based on the sampled data. In response to detecting the misalignment, the calibration control component calibrates the first sampler clock using a second sampler clock and a third sampler clock.


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