The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 02, 2021

Filed:

Sep. 05, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Gerben Doornbos, Kessel-Lo, BE;

Marcus Johannes Henricus Van Dal, Linden, BE;

Timothy Vasen, Tervuren, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 51/05 (2006.01); H01L 27/28 (2006.01); H01L 51/00 (2006.01); H01L 51/10 (2006.01);
U.S. Cl.
CPC ...
H01L 51/0558 (2013.01); H01L 27/283 (2013.01); H01L 51/002 (2013.01); H01L 51/003 (2013.01); H01L 51/0012 (2013.01); H01L 51/0013 (2013.01); H01L 51/0018 (2013.01); H01L 51/0048 (2013.01); H01L 51/055 (2013.01); H01L 51/105 (2013.01); H01L 51/0525 (2013.01); H01L 51/0529 (2013.01);
Abstract

In a method of forming a gate-all-around field effect transistor (GAA FET), a fin structure including carbon nanotubes (CNTs) embedded in a semiconductor layer is formed, a sacrificial gate structure is formed over the fin structure, the semiconductor layer is doped at a source/drain region of the fin structure, an interlayer dielectric (ILD) layer is formed over the doped source/drain region and the sacrificial gate structure, a source/drain opening is formed by patterning the ILD layer, and a source/drain contact layer is formed over the doped source/drain region of the fin structure.


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