The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 02, 2021

Filed:

Jul. 09, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Chia-Cheng Ho, Hsinchu, TW;

Hui-Ting Lu, Zhudong Township, TW;

Pei-Lun Wang, Zhubei, TW;

Yu-Chang Jong, Hsinchu, TW;

Jyun-Guan Jhou, Taoyuan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 29/78 (2006.01); H01L 23/495 (2006.01); H01L 29/66 (2006.01); H01L 21/761 (2006.01); H01L 29/417 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7816 (2013.01); H01L 21/761 (2013.01); H01L 23/49562 (2013.01); H01L 23/49575 (2013.01); H01L 29/402 (2013.01); H01L 29/407 (2013.01); H01L 29/4175 (2013.01); H01L 29/66659 (2013.01); H01L 29/66681 (2013.01); H01L 29/66689 (2013.01); H01L 29/7835 (2013.01); H01L 29/1045 (2013.01); H01L 29/1087 (2013.01);
Abstract

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a gate structure disposed over a substrate between a source region and a drain region. A first inter-level dielectric (ILD) layer is disposed over the substrate and the gate structure and a second ILD layer is disposed over the first ILD layer. A field plate etch stop structure is between the first ILD layer and the second ILD layer. A field plate extends from an uppermost surface of the second ILD layer to the field plate etch stop structure. A plurality of conductive contacts extend from the uppermost surface of the second ILD layer to the source region and the drain region.


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