The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 02, 2021
Filed:
May. 22, 2019
Applicants:
Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;
Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;
Inventors:
Huan Yun Zhang, Shanghai, CN;
Jian Wu, Shanghai, CN;
Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/308 (2006.01); H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 29/10 (2006.01); H01L 29/08 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0673 (2013.01); H01L 21/0217 (2013.01); H01L 21/02236 (2013.01); H01L 21/02532 (2013.01); H01L 21/308 (2013.01); H01L 21/823412 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 27/0886 (2013.01); H01L 29/0847 (2013.01); H01L 29/1033 (2013.01); H01L 29/42392 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01); H01L 29/7843 (2013.01); H01L 29/6659 (2013.01);
Abstract
Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate having a first region and a second region; forming first nanowires over the first region of the semiconductor substrate; forming second nanowires with a diameter smaller than a diameter of the first nanowires over the second region of the semiconductor substrate; forming a first gate layer around the first nanowires; and forming a second gate layer around the second nanowires.