The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 02, 2021

Filed:

Mar. 29, 2019
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventors:

Chun-Yuan Lo, Hsinchu County, TW;

Shih-Chen Wang, Hsinchu County, TW;

Wen-Hao Ching, Hsinchu County, TW;

Chih-Hsin Chen, Hsinchu County, TW;

Wei-Ren Chen, Hsinchu County, TW;

Assignee:

EMEMORY TECHNOLOGY INC., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11517 (2017.01); G11C 16/04 (2006.01); G11C 16/12 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); H01L 27/11524 (2017.01); H01L 49/02 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/788 (2006.01); H01L 27/11519 (2017.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11517 (2013.01); G11C 16/0416 (2013.01); G11C 16/0433 (2013.01); G11C 16/10 (2013.01); G11C 16/12 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 28/40 (2013.01); H01L 29/1095 (2013.01); H01L 29/42324 (2013.01); H01L 29/42328 (2013.01); H01L 29/788 (2013.01); H01L 29/7885 (2013.01); G11C 2216/04 (2013.01); H01L 29/4916 (2013.01);
Abstract

A multi-time programming non-volatile memory includes a select transistor, a floating gate transistor, a switch transistor, a capacitor and an erase gate element. The select transistor is connected with a select line and a source line. The floating gate transistor includes a floating gate. The floating gate transistor is connected with the select transistor. The switch transistor is connected with a word line, the floating gate transistor and a bit line. A first terminal of the capacitor is connected with the floating gate. A second terminal of the capacitor is connected with a control line. The erase gate element includes the floating gate, a gate oxide layer and a p-type region. The erase gate element is connected with an erase line. The floating gate of the erase gate element at least includes an n-type floating gate part.


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