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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11164878 B1

PDFFull Text
Expired
Date of Patent:
Nov. 02, 2021

Filed:

Jan. 30, 2020

Interconnect and memory structures having reduced topography variation formed in the beol

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Chih-Chao Yang, Glenmont, NY (US);

Baozhen Li, South Burlington, VT (US);

Raghuveer Reddy Patlolla, Guilderland, NY (US);

Cornelius Brown Peethala, Slingerlands, NY (US);

Assignee:

International Business Machines Corporation, Armonk, NY (US);

Attorneys:

Scully, Scott, Murphy & Presser, P.C.

L. Jeffrey Kelly, Esq.

Primary Examiner:

Steven H Loke

Assistant Examiner:

Juanita B Rhodes

Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 27/24 (2006.01); H01L 27/22 (2006.01); H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10897 (2013.01); H01L 27/088 (2013.01); H01L 27/222 (2013.01); H01L 27/2481 (2013.01);
Abstract

Interconnect structures or memory structures are provided in the BEOL in which topography variation is reduced. Reduced topography variation is achieved by providing a structure that includes a first dielectric capping layer that has a planar topmost surface and/or a second dielectric capping layer that has a planar topmost surface. The first dielectric capping layer has a non-planar bottom surface that contacts both a recessed surface of an interconnect dielectric material layer and a planar topmost surface of at least one electrically conductive structure that is embedded in the interconnect dielectric material layer.

Find Patent Forward Citations

Yang, Chih-Chao. (2021). Interconnect and memory structures having reduced topography variation formed in the beol (U.S. Patent No. 11164878). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11164878

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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