The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 02, 2021

Filed:

Oct. 07, 2018
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Dietrich Bonart, Bad Abbach, DE;

Ludger Borucki, Munich, DE;

Martina Debie, Bogen, DE;

Bernhard Weidgans, Bernhardswald, DE;

Assignee:

INFINEON TECHNOLOGIES AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/05 (2013.01); H01L 24/03 (2013.01); H01L 24/06 (2013.01); H01L 24/13 (2013.01); H01L 24/29 (2013.01); H01L 24/33 (2013.01); H01L 24/83 (2013.01); H01L 2224/0345 (2013.01); H01L 2224/03614 (2013.01); H01L 2224/03901 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04026 (2013.01); H01L 2224/05083 (2013.01); H01L 2224/05139 (2013.01); H01L 2224/05144 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05155 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05172 (2013.01); H01L 2224/05184 (2013.01); H01L 2224/05187 (2013.01); H01L 2224/05564 (2013.01); H01L 2224/05582 (2013.01); H01L 2224/05639 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/13026 (2013.01); H01L 2224/26145 (2013.01); H01L 2224/291 (2013.01); H01L 2224/33181 (2013.01); H01L 2224/8384 (2013.01); H01L 2224/83447 (2013.01); H01L 2224/83815 (2013.01); H01L 2924/1203 (2013.01); H01L 2924/1306 (2013.01); H01L 2924/3841 (2013.01);
Abstract

Various embodiments provide a semiconductor chip, wherein the semiconductor chip comprises a first contact area and a second contact area both formed at a frontside of the semiconductor chip; a passivation layer arranged at the frontside between the first contact area and the second contact area; and a contact stack formed over the frontside of the semiconductor chip and comprising a plurality of layers, wherein at least one layer of the plurality of layers is removed from the passivation layer and boundary regions of the contact areas being adjacent to the passivation layer and wherein at least one another layer of the plurality of different layer is present in the boundary region of the contact areas adjoining the passivation layer.


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