logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11163530 B1

PDFFull Text
Date of Patent:
Nov. 02, 2021

Filed:

Mar. 22, 2018

Programmable-logic-directed multiplier mapping

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Martin Langhammer, Alderbury, GB;

Gregg William Baeckler, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

Fletcher Yoder, PC

Primary Examiner:

Emily E Larocque

Int. Cl.
CPC ...
G06F 7/53 (2006.01); G06F 7/544 (2006.01); G06F 30/34 (2020.01); G06N 20/00 (2019.01); G06F 30/327 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 111/04 (2020.01); G06F 111/20 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 7/5312 (2013.01); G06F 7/5306 (2013.01); G06F 7/5443 (2013.01); G06F 30/327 (2020.01); G06F 30/34 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06N 20/00 (2019.01); G06F 2111/04 (2020.01); G06F 2111/20 (2020.01); G06F 2119/12 (2020.01);
Abstract

Multiplier circuitry includes first combinatorial circuitry configured to perform a combinatorial function, based at least in part on redundant form arithmetic, to generate a first subset of two or more partial products. The two or more partial products are based at least in part on a first input to the multiplier circuitry and a second input to the multiplier circuitry. The multiplier circuitry also includes a carry chain that includes a second combinatorial circuitry configured to generate a second subset of the two or more partial products based at least in part on the first input and the second input. Furthermore, the carry chain includes one or more binary ripple-carry adders configured to generate a product of the multiplier circuitry based at least in part on a sum of the two or more partial products.

Find Patent Forward Citations

Loading…