The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 02, 2021

Filed:

Apr. 04, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Tarakesava Reddy Koki, Bangalore, IN;

Phani Kumar Alaparthi, Benguluru, IN;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06K 5/04 (2006.01); G11B 5/00 (2006.01); G11B 20/20 (2006.01); G01R 31/317 (2006.01); H03K 5/01 (2006.01); H05K 1/02 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31725 (2013.01); G01R 31/3171 (2013.01); G01R 31/31706 (2013.01); H03K 5/01 (2013.01); H05K 1/0245 (2013.01); H03K 2005/00026 (2013.01);
Abstract

A processor includes a transmitter to transmit, to a receiver, a differential pair of signals including a positive signal transmitted across a positive conductor and a negative signal transmitted across a negative conductor. A first programmable analog delay circuit is coupled to the positive conductor to provide a first delay to the positive signal and a second programmable analog delay circuit is coupled to the negative conductor to provide a second delay to the negative signal. A controller receives data based on a bit error rate (BER) of the differential pair of signals as measured by a bit error checker of the receiver. In response to determining the BER is less than a threshold BER, the controller stores a first delay value to program the first delay and store a second delay value to program the second delay.


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