The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 26, 2021

Filed:

Jan. 30, 2020
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Adrien Benoit Ille, Unterhaching, DE;

Claudia Kupfer, Munich, DE;

Gernot Langguth, Oberhaching, DE;

Assignee:

INFINEON TECHNOLOGIES AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H 9/04 (2006.01);
U.S. Cl.
CPC ...
H02H 9/046 (2013.01);
Abstract

In accordance with an embodiment, a method for protecting a circuit includes: receiving a stress caused by an electrostatic discharge (ESD) event from a first node; limiting a current using a current limiting element coupled between the first node and a second node connected to the circuit; and limiting a voltage on the second node caused by the ESD event using a protection circuit including at least one MOS transistor having a load path coupled to the second node, where the at least one MOS transistor is disposed in a well, and a bias circuit coupled to a gate and a bulk connection of the at least one MOS transistor and a supply node.


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