The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 26, 2021
Filed:
Oct. 30, 2018
Applicant:
International Business Machines Corporation, Armonk, NY (US);
Inventors:
Kevin W. Brew, Albany, NY (US);
Iqbal Rashid Saraf, Cobleskill, NY (US);
Injo Ok, Loudonville, NY (US);
Nicole Saulnier, Albany, NY (US);
Praneet Adusumilli, Somerset, NJ (US);
Assignee:
International Business Machines Corporation, Armonk, NY (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01); G11C 13/00 (2006.01); G11C 11/56 (2006.01); H01L 21/033 (2006.01); H01L 21/027 (2006.01); H01L 21/3213 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 45/1253 (2013.01); G11C 13/0004 (2013.01); G11C 13/0007 (2013.01); G11C 13/0011 (2013.01); H01L 21/0276 (2013.01); H01L 21/0332 (2013.01); H01L 45/06 (2013.01); H01L 45/085 (2013.01); H01L 45/124 (2013.01); H01L 45/1683 (2013.01); G11C 11/5685 (2013.01); H01L 21/32139 (2013.01); H01L 21/76838 (2013.01); H01L 45/144 (2013.01); H01L 45/147 (2013.01);
Abstract
A method for manufacturing a semiconductor device includes forming a memory element in a dielectric layer. A first conductive layer is deposited on the dielectric layer and the memory element by atomic layer deposition, and a second conductive layer is deposited on the first conductive layer by physical vapor deposition. In the method, the first and second conductive layers are patterned into an electrode on the memory element.