The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 26, 2021

Filed:

Aug. 29, 2019
Applicant:

Fuji Electric Co., Ltd., Kawasaki, JP;

Inventor:

Akimasa Kinoshita, Matsumoto, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 27/06 (2006.01); H01L 29/16 (2006.01); H01L 29/49 (2006.01); H01L 29/78 (2006.01); H01L 29/43 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4236 (2013.01); H01L 27/0629 (2013.01); H01L 29/1608 (2013.01); H01L 29/4238 (2013.01); H01L 29/435 (2013.01); H01L 29/4983 (2013.01); H01L 29/7811 (2013.01); H01L 29/7813 (2013.01);
Abstract

A gate pad includes a first portion disposed in a gate pad region and a second portion continuous with the first portion and disposed in a gate resistance region. The gate pad has a planar shape in which the second portion protrudes from the first portion. A gate polysilicon layer provided on a front surface of a semiconductor substrate via a gate insulating film is disposed between the semiconductor substrate and an interlayer insulating film, has a surface area that is at least equal to a surface area of the gate pad, and faces the gate pad in a depth direction. The gate polysilicon layer has a planar outline similar to that of the gate pad and includes continuous first and second portions, the first portion facing the first portion of the gate pad overall, and a second portion facing the second portion of the gate pad.


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