The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 26, 2021

Filed:

Feb. 12, 2020
Applicant:

Zhuhai Chuangfeixin Technology Co., Ltd., Zhuhai, CH;

Inventors:

Li Li, Femont, CA (US);

Zhigang Wang, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/112 (2006.01); H01L 27/11502 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11206 (2013.01); H01L 27/11246 (2013.01); H01L 27/11502 (2013.01);
Abstract

An antifuse One-Time-Programmable memory cell includes a substrate, a select transistor formed on the substrate, and an antifuse capacitor formed on the substrate. The select transistor includes a first gate dielectric layer formed on the substrate, a first gate formed on the gate dielectric layer, a first high-voltage junction formed in the substrate, and a second high-voltage junction formed in the substrate. A source and a drain for the select transistor are formed by the first high-voltage junction and the second high-voltage junction. The antifuse capacitor includes a second gate dielectric layer formed on the substrate, a second gate formed on the gate dielectric layer, a third high-voltage junction formed in the substrate, and a fourth high-voltage junction formed in the substrate. A source and a drain for the antifuse capacitor are respectively formed by the third high-voltage junction and the fourth high-voltage junction.


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