The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 26, 2021

Filed:

Jan. 19, 2018
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Chang Hwi Lee, Seoul, KR;

Hee Jeong Son, Gyeonggi-do, KR;

Ki Ryong Jung, Gyeonggi-do, KR;

Seung Yeop Lee, Gyeonggi-do, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H02H 9/04 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0266 (2013.01); H01L 27/027 (2013.01); H01L 27/0255 (2013.01); H01L 27/0292 (2013.01); H02H 9/046 (2013.01); H01L 27/088 (2013.01);
Abstract

A semiconductor integrated circuit device may include a pad, a first voltage protection unit and a second voltage protection unit. The first voltage protection unit may be connected with the pad. The first voltage protection unit may be configured to maintain a turn-off state when a test voltage having a negative level may be applied from the pad. The second voltage protection unit may be connected between the first voltage protection unit and a ground terminal. The second voltage protection unit may be turned-on when an electrostatic voltage having a positive level may be applied from the pad. The second voltage protection unit may include a plurality of gate positive p-channel metal oxide semiconductor (GPPMOS) transistors serially connected with each other.


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