The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 26, 2021

Filed:

Jul. 22, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Yonghyuk Choi, Suwon-si, KR;

Jae-Duk Yu, Seoul, KR;

Kang-Bin Lee, Suwon-si, KR;

Sang-Won Shim, Seoul, KR;

Bongsoon Lim, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 16/34 (2006.01); H01L 25/065 (2006.01); H01L 25/18 (2006.01); H01L 23/00 (2006.01); H01L 27/11582 (2017.01); H01L 27/11556 (2017.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/349 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/08145 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01);
Abstract

Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.


Find Patent Forward Citations

Loading…