The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 26, 2021

Filed:

Jan. 24, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Prashant Chaudhari, Folsom, CA (US);

Arthur Runyan, Folsom, CA (US);

Michael Derr, El Dorado Hills, CA (US);

Jonathan Oder, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 5/391 (2006.01); G09G 5/36 (2006.01); G06F 1/08 (2006.01); H03C 3/09 (2006.01); H03L 7/07 (2006.01);
U.S. Cl.
CPC ...
G09G 5/391 (2013.01); G06F 1/08 (2013.01); G09G 5/363 (2013.01); G09G 2310/08 (2013.01); G09G 2340/0435 (2013.01); G09G 2370/12 (2013.01); H03C 3/0966 (2013.01); H03L 7/07 (2013.01);
Abstract

Upon external display configuration change, a graphics display driver or any suitable hardware or software modifies the clock frequency of the processor core (e.g., graphics processor core) display engine. The graphics display driver or any suitable hardware or software reprograms the core display clock PLL (CDCLK PLL) to a new frequency, without any dead clocks during such frequency change. A divide-by-2 divider changes the frequency of the PLL on the fly or dynamically. The technique may not require the PLL to be turned off and turned back again at all.


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