The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 26, 2021

Filed:

Dec. 29, 2017
Applicant:

Gowin Semiconductor Corporation, GuangZhou, CN;

Inventors:

Jinghui Zhu, San Jose, CA (US);

San-Ta Kow, Foshan, CN;

Tun Jun Gao, Foshan, CN;

Diwakar Chopperla, Fremont, CA (US);

Chienkuang Chen, Foshan, CN;

Ning Song, Cupertino, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/10 (2006.01); H03K 19/177 (2020.01); G06F 12/06 (2006.01); G06F 13/42 (2006.01); G06F 13/12 (2006.01);
U.S. Cl.
CPC ...
G06F 13/102 (2013.01); G06F 12/0638 (2013.01); G06F 13/12 (2013.01); G06F 13/4282 (2013.01); H03K 19/177 (2013.01); G06F 2212/205 (2013.01);
Abstract

The present application discloses a system level integrated circuit chip, comprising a fixed logic module and a Programmable Logic Module; the fixed logic module comprising a CPU module, a non-volatile memory module, a high speed data transmission module, an analogue-to-digital and/or digital-to-analogue conversion module; the Programmable Logic Module comprising a user-defined field programmable gate array and a programmable control module; the CPU module is interconnected with the user-defined field programmable gate array and the programmable control module; the non-volatile memory is interconnected with the user-defined field programmable gate array and the programmable control module; the analogue-to-digital and/or digital-to-analogue conversion module are connected with the user-defined field programmable gate array; and the high speed data transmission module is interconnected with the user-defined field programmable gate array. The present application solves the problem of the combination of a variety of different devices and the integration of processing capabilities with different applications.


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