The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 19, 2021

Filed:

Jan. 27, 2020
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Gaurav Thareja, Santa Clara, CA (US);

Xuebin Li, Sunnyvale, CA (US);

Abhishek Dube, Fremont, CA (US);

Yi-Chiau Huang, Fremont, CA (US);

Andy Lo, Saratoga, CA (US);

Patricia M. Liu, Saratoga, CA (US);

Sanjay Natarajan, Portland, OR (US);

Saurabh Chopra, Santa Clara, CA (US);

Assignee:

APPLIED MATERIALS, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/45 (2006.01); H01L 29/08 (2006.01); H01L 29/40 (2006.01); H01L 29/78 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 29/456 (2013.01); H01L 29/0847 (2013.01); H01L 29/401 (2013.01); H01L 29/41791 (2013.01); H01L 29/785 (2013.01);
Abstract

The present disclosure generally relates to methods for forming a semiconductor device, a semiconductor device, and a processing chamber. The method includes forming a source/drain region in a processing system, forming a doped semiconductor layer on the source/drain region in the processing system, forming a metal silicide layer, forming a dielectric material, forming a trench in the dielectric material, and filling the trench with a conductor. The source/drain region, the doped semiconductor layer, and the metal silicide layer are formed without breaking vacuum. A semiconductor device includes a plurality of layers, and the semiconductor device has reduced contact resistance. A processing system is configured to perform the method and form the semiconductor device. Embodiments of the present disclosure enable formation of a source/drain contact with reduced contact resistance by using integrated processes, which allows various operations of the source/drain contact formation to be performed within the same processing system.


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