The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 19, 2021

Filed:

Sep. 23, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Hsing-Lien Lin, Hsin-Chu, TW;

Chii-Ming Wu, Taipei, TW;

Chia-Shiung Tsai, Hsin-Chu, TW;

Chung-Yi Yu, Hsin-Chu, TW;

Rei-Lin Chu, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 23/52 (2006.01); H01L 49/02 (2006.01); H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 23/64 (2006.01); H01L 27/22 (2006.01);
U.S. Cl.
CPC ...
H01L 28/60 (2013.01); H01L 21/0234 (2013.01); H01L 21/02252 (2013.01); H01L 21/02315 (2013.01); H01L 21/76825 (2013.01); H01L 21/76841 (2013.01); H01L 23/642 (2013.01); H01L 27/224 (2013.01);
Abstract

Various embodiments of the present application are directed towards a method for forming a metal-insulator-metal (MIM) capacitor comprising an enhanced interfacial layer to reduce breakdown failure. In some embodiments, a bottom electrode layer is deposited over a substrate. A native oxide layer is formed on a top surface of the bottom electrode layer and has a first adhesion strength with the top surface. A plasma treatment process is performed to replace the native oxide layer with an interfacial layer. The interfacial layer is conductive and has a second adhesion strength with the top surface of the bottom electrode layer, and the second adhesion strength is greater than the first adhesion strength. An insulator layer is deposited on the interfacial layer. A top electrode layer is deposited on the insulator layer. The top and bottom electrode layers, the insulator layer, and the interfacial layer are patterned to form a MIM capacitor.


Find Patent Forward Citations

Loading…