The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 19, 2021
Filed:
Nov. 12, 2020
X-celeprint Limited, Dublin, IE;
Joseph Carr, Chapel Hill, NC (US);
Ronald S. Cok, Rochester, NY (US);
X-Celeprint Limited, Dublin, IE;
Abstract
A monolithic multi-FET transistor comprises an epitaxial layer disposed on a dielectric layer. The epitaxial layer comprises a crystalline semiconductor material and a multi-FET area. An isolation structure surrounds the multi-FET area and divides the multi-FET area into separate FET portions. A gate disposed on a gate dielectric extends over each FET portion. A source and a drain are each disposed on opposite sides of the gate on the epitaxial layer within each FET portion. Each gate, source, and drain comprise a separate electrical conductor and the gate, source, drain, and epitaxial layer within each FET portion form a field-effect transistor. Gate, source, and drain contacts electrically connect the gates, sources, and drains of the separate FET portions, respectively. At least the sources or drains of two neighboring FET portions are disposed in common over at least a portion of the isolation structure dividing the two neighboring FET portions.