The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 19, 2021

Filed:

Dec. 18, 2019
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Gary D. Hamor, Mead, CO (US);

Michael T. Brady, Loveland, CO (US);

William A. Marcus, Frederick, CO (US);

Larry J. Koudele, Erie, CO (US);

Assignee:

MICRON TECHNOLOGY, INC., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/44 (2006.01); G11C 29/32 (2006.01); G11C 29/02 (2006.01); G06F 11/30 (2006.01); G11C 29/56 (2006.01);
U.S. Cl.
CPC ...
G11C 29/44 (2013.01); G06F 11/3037 (2013.01); G06F 11/3062 (2013.01); G11C 29/022 (2013.01); G11C 29/32 (2013.01); G11C 29/56 (2013.01); G11C 2029/5602 (2013.01);
Abstract

A processing device of a memory device test resource detects that a memory sub-system has engaged with a first memory sub-system interface port and a second memory sub-system interface port of the memory device test resource. The processing device causes a power supply signal to be transmitted from the memory device test resource to the memory sub-system via the first memory sub-system interface port. The processing device identifies a test to be performed for a memory device of the memory sub-system, where the test includes one or more test instructions to be executed in performance of the test. The processing device causes the one or more test instructions to be transmitted from the memory device test resource to the memory sub-system via the second memory sub-system interface port, where the test is performed by the one or more test instructions executing at the memory sub-system.


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