The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 19, 2021

Filed:

Dec. 07, 2018
Applicants:

Stmicroelectronics SA, Montrouge, FR;

Institut Polytechnique DE Grenoble, Grenoble, FR;

Inventors:

Sophie Germain, Grenoble, FR;

Sylvain Engels, Meylan, FR;

Laurent Fesquet, Sassenage, FR;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/00 (2013.01); G06F 21/72 (2013.01); G06F 21/75 (2013.01); G06F 21/60 (2013.01); H03K 5/14 (2014.01); G06F 21/77 (2013.01); H03K 5/00 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
G06F 21/72 (2013.01); G06F 21/602 (2013.01); G06F 21/755 (2017.08); G06F 21/77 (2013.01); H03K 5/14 (2013.01); H03K 19/20 (2013.01); H03K 2005/00019 (2013.01);
Abstract

An asynchronous pipeline circuit includes: a first processing stage including a first data latch configured to generate a request signal; a second processing stage downstream the first processing stage and including a second data latch; and a programmable delay line coupled between the first data latch and the second processing stage. The programmable delay line is configured to receive the request signal from the first data latch and to generate a delayed request signal by randomly delaying the request signal on each data transfer from the first data latch to the second data latch.


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