logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11145565 B1

PDFFull Text
Date of Patent:
Oct. 12, 2021

Filed:

Jun. 10, 2020

Method of fabricating a chip package module with improve heat dissipation effect

Applicant:

Youngtek Electronics Corporation, Hsinchu, TW;

Inventors:

Hsi-Ying Yuan, Miaoli County, TW;

Tung-Chuan Wang, Taoyuan, TW;

Chun-Yuan Hou, Hsinchu County, TW;

Ping-Lung Wang, Hsinchu, TW;

Tzu-kuei Wen, Hsinchu, TW;

Assignee:

YOUNGTEK ELECTRONICS CORPORATION, Hsinchu, TW;

Attorney:

Li & Cai Intellectual Property (USA) Office

Primary Examiner:

Alonzo Chambliss

Int. Cl.
CPC ...
H01L 23/053 (2006.01); H01L 23/34 (2006.01); H01L 23/48 (2006.01); H01L 21/00 (2006.01); H05K 7/20 (2006.01); H05K 7/00 (2006.01); H01L 23/367 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 21/683 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/367 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/4871 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 23/3107 (2013.01); H01L 23/3121 (2013.01); H01L 23/34 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 2221/68309 (2013.01); H01L 2221/68372 (2013.01); H01L 2221/68386 (2013.01); H01L 2224/214 (2013.01);
Abstract

A power chip package module and a manufacturing method thereof are provided. In the manufacturing method, a temporary carrier having an alignment pattern is provided, in which the temporary carrier includes a base and a peelable adhesive material disposed on the base. Thereafter, a circuit board having an accommodating space passing therethrough is disposed on the temporary carrier according to the alignment pattern. Furthermore, a chip is disposed in the accommodating space with an active surface thereof facing the temporary carrier according to the alignment pattern, in which the chip is fixed on the temporary carrier by the peelable adhesive material. The accommodating space is filled with a molding material to form an initial package structure. The initial package structure is separated from the temporary carrier, and then an electrically and thermally conductive layer is formed on a bottom surface of the chip and is in contact therewith.

Find Patent Forward Citations

Loading…