The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 12, 2021

Filed:

Dec. 03, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Shankar Natarajan, Folsom, CA (US);

Sriram Natarajan, Folsom, CA (US);

Arun S. Athreya, Folsom, CA (US);

Venkata S. Surampudi, Folsom, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 29/38 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 29/883 (2013.01); G11C 29/38 (2013.01); G11C 16/0483 (2013.01);
Abstract

An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control a persistent storage media including a first media to store one or more source blocks of data and a second media to store one or more destination blocks of data, determine if an error rate associated with a read of a particular destination block of the one or more destination blocks exceeds a threshold error rate, identify a particular source block of the one or more source blocks which corresponds to erroneous data in the particular destination block, determine which of the particular source block and the particular destination block is a failed block, and retire the failed block. Other embodiments are disclosed and claimed.


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