The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 12, 2021
Filed:
Mar. 24, 2020
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Davide Mantegazza, Palo Alto, CA (US);
Kiran Pangal, Fremont, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); G11C 29/12 (2006.01); G11C 29/50 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G11C 13/004 (2013.01); G11C 13/0004 (2013.01); G11C 13/0038 (2013.01); G11C 13/0061 (2013.01); G11C 29/12005 (2013.01); G11C 29/44 (2013.01); G11C 29/50004 (2013.01); G11C 2213/71 (2013.01);
Abstract
Examples may include techniques to mitigate errors during a read operation to a memory cell of a memory array. Examples include selecting the memory cell and applying one of multiple demarcation read voltages for respective multiple time intervals to sense a state of a resistive storage element of the memory cell. Examples also include applying a bias voltage to the memory cell following a sense interval to mitigate read disturb to the resistive storage element incurred while the one of the multiple demarcation read voltages was applied to the memory cell.