Physically unclonable function architecture including memory cells with parallel-connected access transistors and common write wordlines

Abstract

Disclosed is a memory cell including parallel-connected first access transistors and a first variable resistor in series between a bitline and a source line and parallel-connected second access transistors and a second variable resistor in series between the bitline and the source line. A write wordline controls one pair of first and second access transistors so that, during an initialization mode, the resistors are concurrently subjected to the same write bias conditions for one-time programming to switch from an unprogrammed state (where the resistors have the same first resistance state) to a programmed state (where one resistor has switched to a second resistance state and a bit is stored). Discrete first and second read wordlines control another pair of first and second access transistors to enable discrete read processes associated with the first and second variable resistors. Also disclosed are an associated circuit (e.g., a PUF) and a method.