The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 12, 2021
Filed:
Dec. 18, 2019
Synopsys, Inc., Mountain View, CA (US);
Jun Wang, Shanghai, CN;
Yun-Jui Li, Shanghai, CN;
Bin Xu, Shanghai, CN;
Cheng-Ming Wu, Hsinchu, TW;
Yu Fan Lu, Kaohsiung, TW;
Hu Cai, Shanghai, CN;
Yuting Fu, Hsinchu, TW;
Hwei-Tseng Wang, Hsinchu, TW;
Sui Zheng, Shanghai, CN;
Jeong-Tyng Li, Saratoga, CA (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
Techniques and systems for implementing a general extensible layer mapping approach that maps between integrated circuit (IC) design database layers and process layers are described. A first IC design layout having in-design layers can be converted into a second IC design layout having derived layers, wherein said converting comprises mapping the in-design layers to the derived layers by applying a set of layer derivation rules to shapes in the IC design layout, and wherein the set of layer derivation rules implements a one-to-many mapping between the in-design layers and the derived layers. Next, a one-to-one mapping between the derived layers and process layers used in a parasitic extraction tool can be generated. Parasitic extraction on the IC design layout then be performed by providing the second IC design layout and the one-to-one mapping to the parasitic extraction tool.