The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 12, 2021
Filed:
Aug. 08, 2019
Nxp Usa, Inc., Austin, TX (US);
Stefan Doll, Munich, DE;
Thomas Henry Luedeke, Oberbergkirchen, DE;
Nikila Krishnamoorthy, Chennai, IN;
Hubert Glenn Carson, Jr., Austin, TX (US);
Anurag Jindal, Austin, TX (US);
Hilario Manuel Garza, Cedar Park, TX (US);
Kamel Musa Khalaf, Austin, TX (US);
Joel Ray Knight, Austin, TX (US);
Adrian Lee Carleton, Austin, TX (US);
NXP USA, Inc., Austin, TX (US);
Abstract
A fully digital integrated circuit apparatus () and method () are provided for generating a test mode enable signal with a digital non-resettable state retention storage circuit () connected to store an authentication control pattern for authorizing test mode access to a secure circuit, a digital safety interlock gate circuit () connected to store a safety interlock gate setting that may be accessed independently from a test mode enable signal, and combinatorial logic circuitry () for generating the test mode enable signal only when the interlock safety gate setting is set to a first value and the digital non-resettable state retention storage circuit stores the authentication control code.