The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 12, 2021

Filed:

Aug. 07, 2019
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Daniel B. Penney, Wylie, TX (US);

Liang Chen, Allen, TX (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 11/40 (2006.01); G11C 11/4096 (2006.01); G11C 11/408 (2006.01); G11C 11/4076 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0611 (2013.01); G06F 3/0673 (2013.01); G11C 11/4076 (2013.01); G11C 11/4087 (2013.01); G11C 11/4096 (2013.01);
Abstract

A host device and memory device function together to perform internal write leveling of a data strobe with a write command within the memory device. The memory device includes a command interface configured to receive write commands from the host device. The memory device also includes an input-output interface configured to receive the data strobe from the host device. The memory device also includes internal write circuitry configured to launch an internal write signal based at least in part on the write commands. The launch of the internal write signal is based at least in part on an indication from the host device that indicates when to launch the internal write signal relative to a cas write latency (CWL) for the memory device.


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