The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 05, 2021
Filed:
May. 15, 2020
Cadence Design Systems, Inc., San Jose, CA (US);
Tulio Paschoalin Leao, Betim, BR;
Petros Daniel Fernandes de Medeiros Félix, Belo Horizonte, BR;
Julia Pinheiro de Oliveira, Belo Horizonte, BR;
Arthur Ribeiro Araujo, Belo Horizonte, BR;
Lucas Martins Chaves, Belo Horizonte, BR;
Andrei dos Santos Silva, Belo Horizonte, BR;
Pablo Nunes Agra Belmonte, Belo Horizonte, BR;
CADENCE DESIGN SYSTEMS, INC., San Jose, CA (US);
Abstract
A formal verification EDA application can be configured to receive a circuit design of an IC chip. The circuit design of the IC chip comprises a set of properties for the IC chip and constraints for the IC chip. The formal verification EDA application generates an array of CNF files based on the circuit design of the IC chip. Each CNF file can include a Boolean expression that characterizes a selected property of the set of properties and data fields characterizing initial states for literals in the Boolean expression and the constraints of the IC chip. The formal verification application can also be configured to output the array of CNF files to a hardware prototyping platform. The hardware prototyping platform can be configured to execute a hardware instantiated SAT solver for the Boolean expression in each CNF file in the array of CNF files.