The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 05, 2021
Filed:
May. 09, 2019
Applicant:
Renesas Electronics Corporation, Tokyo, JP;
Inventors:
Tetsuya Iida, Ibaraki, JP;
Yasutaka Nakashiba, Ibaraki, JP;
Assignee:
RENESAS ELECTRONICS CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02B 6/42 (2006.01); H01L 23/00 (2006.01); H04B 10/80 (2013.01); H01L 25/16 (2006.01);
U.S. Cl.
CPC ...
G02B 6/4274 (2013.01); H01L 25/167 (2013.01); G02B 6/42 (2013.01); G02B 6/4206 (2013.01); H01L 24/08 (2013.01); H01L 24/09 (2013.01); H01L 24/80 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/09517 (2013.01); H04B 10/801 (2013.01);
Abstract
The semiconductor module includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes an optical device such as an optical waveguide and wiring formed over the optical device. The second semiconductor chip include semiconductor elements such as MISFET, and wiring formed over the semiconductor elements. A top surface of the first semiconductor chip is laminated with a top surface of the second semiconductor chip such that the first and second wirings are directly contacted with each other.