The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 28, 2021

Filed:

Sep. 23, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Eliezer Tamir, Bait Shemesh, IL;

Ben-Zion Friedman, Jerusalem, IL;

Itamar Levin, Holon, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 12/851 (2013.01); H04L 29/06 (2006.01); H04L 29/08 (2006.01); H04L 12/24 (2006.01); H04L 12/861 (2013.01); H04L 12/835 (2013.01); H04L 12/825 (2013.01); H04L 12/28 (2006.01);
U.S. Cl.
CPC ...
H04L 67/145 (2013.01); H04L 41/0816 (2013.01); H04L 47/24 (2013.01); H04L 47/266 (2013.01); H04L 47/30 (2013.01); H04L 49/9068 (2013.01); H04L 67/025 (2013.01); H04L 69/24 (2013.01); H04L 69/322 (2013.01); H04L 69/323 (2013.01); H04L 69/324 (2013.01); H04L 12/28 (2013.01);
Abstract

Methods and apparatus for supporting active link status during LAN interface reset and reconfigurations. Under one aspect, during normal operations traffic is transmitted over an Ethernet link coupling a first link partner to a second link partner. In response to a network interface re-configuration event, transmission of traffic over the Ethernet link is paused while keeping the Physical layer (PHY) of the Ethernet link active. The configuration of the first link partner is updated while the transmission of traffic is paused and the PHY of the Ethernet link is active. Upon completion of the configuration update, the link partners resume transmission of traffic over the Ethernet link. Additional schemes are provided that support re-configuration of network interfaces that support link and per priority flow control. According to another aspect, separate power domains are used for the PHY and the MAC circuitry, enabling the MAC circuitry to be reset via a power cycle while maintaining power to the PHY circuitry.


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