The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 28, 2021

Filed:

Apr. 17, 2020
Applicant:

Magnachip Semiconductor, Ltd., Cheongju-si, KR;

Inventors:

Jae Hyung Jang, Daejeon, KR;

Jin Yeong Son, Cheongju-si, KR;

Hee Hwan Ji, Daejeon, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/10 (2006.01); H01L 27/06 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7835 (2013.01); H01L 27/0617 (2013.01); H01L 27/0927 (2013.01); H01L 27/0928 (2013.01); H01L 29/0692 (2013.01); H01L 29/1041 (2013.01); H01L 29/1045 (2013.01); H01L 29/42372 (2013.01); H01L 29/66659 (2013.01); H01L 29/0653 (2013.01); H01L 29/665 (2013.01);
Abstract

A semiconductor device includes a substrate, a first P-type well region and a second P-type well region disposed in the substrate, wherein the first P-type well region and the second P-type well region are spaced apart from each other, an N-type source region disposed in the substrate, wherein the N-type source region is disposed spaced apart from the second P-type well region, an N-type drain region disposed in the second P-type well region, an N-type LDD region disposed near the N-type drain region, and a gate insulating layer and a gate electrode on the substrate, wherein the gate electrode partially overlaps the second P-type well region.


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