The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 28, 2021

Filed:

Sep. 26, 2019
Applicant:

Nanya Technology Corporation, New Taipei, TW;

Inventors:

Da-Zen Chuang, Taipei, TW;

Pin-Hsiu Hsieh, Taoyuan, TW;

Chih-Chung Sun, Zhubei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01F 10/32 (2006.01); H01L 23/58 (2006.01); H01L 29/49 (2006.01); H01L 21/28 (2006.01); H01L 29/40 (2006.01); H01L 27/22 (2006.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 43/02 (2006.01); H01L 43/12 (2006.01); G11C 11/16 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10897 (2013.01); G11C 11/161 (2013.01); H01F 10/329 (2013.01); H01F 10/3254 (2013.01); H01L 21/28035 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/585 (2013.01); H01L 27/10814 (2013.01); H01L 27/10823 (2013.01); H01L 27/10876 (2013.01); H01L 27/10885 (2013.01); H01L 27/228 (2013.01); H01L 29/401 (2013.01); H01L 29/4916 (2013.01); H01L 43/02 (2013.01); H01L 43/12 (2013.01);
Abstract

The present disclosure provides a semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate, a memory cell, a first logic transistor, and a second logic transistor. The semiconductor substrate includes a memory region and a logic region. The memory cell is disposed in the memory region. The first logic transistor is disposed in the memory region and disposed adjacent to the memory cell. The second logic transistor is disposed in the logic region. The first logic transistor is configured to control operation of the memory cell in response to a memory control signal provided by the second logic transistor.


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