The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 28, 2021
Filed:
Dec. 19, 2018
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Chi-Wen Liu, Hsinchu, TW;
Chao-Hsiung Wang, Hsinchu, TW;
Assignee:
Taiwan Semiconductor Manafacturing Company, Ltd., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 23/522 (2006.01); H01L 29/94 (2006.01); H01L 27/12 (2006.01); H01L 49/02 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0629 (2013.01); H01L 23/5223 (2013.01); H01L 27/1203 (2013.01); H01L 27/1211 (2013.01); H01L 28/40 (2013.01); H01L 28/60 (2013.01); H01L 28/90 (2013.01); H01L 29/40 (2013.01); H01L 29/94 (2013.01); H01L 2924/0002 (2013.01);
Abstract
An integrated circuit can include a MOM capacitor formed simultaneously with other devices, such as finFETs. A dielectric layer formed on a substrate has a first semiconductor fin therein and a second semiconductor fin therein. Respective top portions of the fins are removed to form respective recesses in the dielectric layer. First and second electrodes are formed in the recesses. The first and second electrodes and the interjacent dielectric layer form a MOM capacitor.