The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 28, 2021

Filed:

Feb. 19, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hakseung Lee, Seoul, KR;

Jinnam Kim, Anyang-si, KR;

Kwangjin Moon, Hwaseong-si, KR;

Eunji Kim, Seoul, KR;

Taeseong Kim, Suwon-si, KR;

Sangjun Park, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 25/18 (2006.01); H01L 21/768 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/76805 (2013.01); H01L 21/76816 (2013.01); H01L 21/76898 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 25/18 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/17181 (2013.01);
Abstract

A semiconductor device includes a semiconductor substrate including at least one semiconductor structure, an interlayer insulating layer disposed on the semiconductor substrate, at least one first via structure penetrating the semiconductor substrate and the interlayer insulating layer, including a first region having a first width at an upper surface of the interlayer insulating layer and a second region extending from the first region and having a second width at a lower surface of the semiconductor substrate, wherein a side surface of the first region and a side surface of the second region have different profiles at a boundary between the first region and the second region, and at least one second via structure penetrating the semiconductor substrate and the interlayer insulating layer and having a third width greater than the first width at an upper surface of the interlayer insulating layer.


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