The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 28, 2021
Filed:
Dec. 20, 2018
Lattice Semiconductor Corporation, Portland, OR (US);
Fulong Zhang, Cupertino, CA (US);
Gordon Hands, San Jose, CA (US);
Satwant Singh, Fremont, CA (US);
Wei Han, Portland, OR (US);
Ravindar Lail, Portland, OR (US);
Joel Copien, Portland, OR (US);
Sreepada Hegade, San Jose, CA (US);
Ming Hui Ding, San Jose, CA (US);
LATTICE SEMICONDUCTOR CORPORATION, Hillsboro, OR (US);
Abstract
Various techniques are provided to implement fast boot for programmable logic devices (PLDs). In one example, a method includes receiving configuration data associated with a PLD. The PLD includes an array of configuration memory cells including logic block memory cells and input/output (I/O) block memory cells associated with the PLD's logic fabric and I/O fabric, respectively. The method further includes programming a subset of the I/O block memory cells with the configuration data, and providing a wakeup signal to activate functionality associated with a portion of the I/O fabric. The method further includes programming remaining configuration memory cells of the array with the configuration data, where the remaining configuration memory cells include at least a subset of the logic block memory cells. The method further includes providing a wakeup signal to activate functionality associated with at least a portion of the logic fabric. Related systems and devices are provided.